? semiconductor components industries, llc, 2001 august, 2001 rev. 4 1 publication order number: mc100ep140/d mc100ep140 3.3vecl phase-frequency detector the mc100ep140 is a three state phase frequencydetector intended for phaselocked loop applications which require a minimum amount of phase and frequency difference at lock. since the part is designed with fully differential internal gates, the noise is reduced throughout the circuit, especially at high speeds. the basic operation of a phase/frequency detector (pfd) is to acompareo an incoming signal (feedback) to a set reference signal. when the reference (r) and feedback (fb) inputs are unequal in frequency and/or phase, the differential up (u) and down (d) outputs will provide pulse streams which, when subtracted and integrated, provide an error voltage for control of a vco. detector states of operation are shown in the figure 2 and the state table. the device is packaged in a small outline, surface mount 8lead soic package. the typical output amplitude of the ep140 is 400 mv, allowing faster switching time and greater bandwidth. for proper operation, the input edge rate of the r and fb inputs should be less than 5 ns. more information on phase lock loop operation and application can be found in and8040. the pinout is shown in figure 1, the logic diagram in figure 3, and the typical termination in figure 5. ? 500 ps typical propagation delay ? maximum frequency > 2.1 ghz typical ? fully differential internally ? advanced high band output swing of 400 mv ? transfer gain: 1.0 mv/degree at 1.4 ghz 1.2 mv/degree at 1.0 ghz ? rise and fall time: 100 ps typical ? the 100 series contains temperature compensation ? pecl mode operating range: v cc = 3.0 v to 3.6 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 3.6 v ? open input default state http://onsemi.com device package shipping ordering information mc100ep140d so8 98 units/rail mc100ep140dr2 so8 2500 units/reel marking diagram alyw kp140 kp = mc100ep a = assembly location l = wafer lot y = year w = work week so8 d suffix case 751 1 8 1 8
mc100ep140 http://onsemi.com 2 figure 1. 8lead pinout (top view) figure 2. phase detector logic model 8 1 v cc u 7 2 r u 6 3 fb d 5 4 v ee d pin description pin d, d u, u differential up outputs function differential down outputs v cc v ee negative supply positive supply fb* ecl feedback input r* ecl reference input state table phase detector state input output pump down 212 rfb ud pump up 232 2 21 12 2 2 23 32 2 l l h l l h l l l l l l l h l l l h h l l l h l l h l l l l l l * pins will default low when left open. 3 u = h d = l 1 2 u = l d = h u = l d = l pump down pump up fb fb fb rr r figure 3. logic diagram u r u u a fb d b b a reset reset c d a c d b reset reset c a b d d d s r ff u r s ff d v ee
mc100ep140 http://onsemi.com 3 attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1.) level 1 flammability rating oxygen index ul94 code v0 a 1/8o 28 to 34 transistor count 457 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2.) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input volta g e v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w q jc thermal resistance (junction to case) std bd 8 soic 41 to 44 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur. 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 70 85 60 74 90 63 78 93 ma v oh output high voltage (note 4.) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 4.) 1755 1880 2005 1755 1880 2005 1755 1880 2005 mv v ih input high voltage (single ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single ended) 1355 1675 1355 1675 1355 1675 mv i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 0.3 v. 4. all loading with 50 ohms to v cc 2.0 volts.
mc100ep140 http://onsemi.com 4 100ep dc characteristics, necl v cc = 0 v, v ee = 3.6 v to 3.0 v (note 5.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 70 85 60 74 90 63 78 93 ma v oh output high voltage (note 6.) 1145 1020 895 1145 1020 895 1145 1020 895 mv v ol output low voltage (note 6.) 1545 1420 1295 1545 1420 1295 1545 1420 1295 mv v ih input high voltage (single ended) 1225 880 1225 880 1225 880 mv v il input low voltage (single ended) 1945 1625 1945 1625 1945 1625 mv i ih input high current 150 150 150 m a i il input low current d d 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 5. input and output parameters vary 1:1 with v cc . 6. all loading with 50 ohms to v cc 2.0 volts. ac characteristics v cc = 0 v; v ee = 3.0 v to 3.6 v or v cc = 3.0 v to 3.6 v; v ee = 0 v (note 7.) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 4. f max /jitter) > 2 > 2 > 2 ghz t plh , t phl propagation delay to r to u, fb to d output differential fb to u, r to d 300 400 450 600 6002 800 325 450 475 650 625 850 350 500 500 700 650 900 ps t jitter cycletocycle jitter (see figure 4. f max /jitter) .2 < 1 .2 < 1 .2 < 1 ps v pp input voltage swing 400 800 1200 400 800 1200 400 800 1200 mv t r t f output rise/fall times q, q (20% 80%) 50 90 180 60 100 200 70 120 220 ps 7. measured using a 750 mv v pp pkpk, 50% duty cycle, clock source. all loading with 50 ohms to v cc 2.0 v. 0 100 200 300 400 500 600 0 400 800 1200 1600 2000 2400 figure 4. f max /jitter frequency (mhz) 1 2 3 4 5 6 ???????????????? ???????????????? ???????????????? (jitter) v outpp (mv) jitter out ps (rms) ?? ??
mc100ep140 http://onsemi.com 5 v tt = v cc 2.0 v figure 5. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices and8040 phase lock loop operation for an updated list of application notes, please see our website at http://onsemi.com.
mc100ep140 http://onsemi.com 6 package dimensions so8 d suffix plastic soic package case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc100ep140 http://onsemi.com 7 notes
mc100ep140 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100ep140/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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